1. Field of the Invention
The present invention relates to digital phase shifting systems configured for outputting a phase-shifted signal relative to a reference clock.
2. Background Art
Newer communications systems require advanced processing of high speed digital signals in order to accommodate precise timing requirements. For example, processor-based communications systems such as HyperTransport™ bus architectures rely on integrated circuits having phase shifting circuits for phase-shifting a clock signal, for example for timing synchronization.
Implementation of digital phase shifting systems in an integrated circuit, however, may suffer from numerous problems that may affect the integrity of the signal to be output. For example, digital systems often rely on binary coding, where a digital value composed of N bits has a range of values from zero to 2N−1. However, reliance on binary coding suffers from the disadvantage of Most Significant Bit (MSB) rollover, where a simultaneous transition in multiple bits due to a change in value (e.g., “7”=0111 to “8”=1000) creates numerous discontinuities in the circuits implementing the digital system, resulting in voltage spikes on the output signal; such voltage spikes may cause transient phase errors that may result in misinterpretation of a clock strobe, data, etc., resulting in errors due to instability of the output signal. Efforts to filter the voltage spikes from the output signal often are not practical in integrated circuits due to the added delay or the increased capacitance.
In addition, implementation of digital phase shifting systems in an integrated circuit may encounter errors due to nonlinearities due to process variations encountered during manufacture of the integrated circuit.
Finally, digital phase shifting systems may suffer from the problem of adding a bias to the reference clock signal that may affect the duty cycle of the output signal.